Designing and fabricating power VDMOS transistors having scaled dimensions but with high current capabilities is limited with respect to nested geometries being formed within an elementary unit in an active area. Moreover, even if it were possible to accurately align structures in submicron spaces, certain contributions to the ON-resistance of the integrated device would still limit the level of performance that can be achieved.
A typical example is the JFET contribution to the resistance in the active area, which depends on the separation distance between contiguous body diffusions. Making two contiguous elementary structures closer together leads to an increase in the packing density, and thus the active perimeter of the device per unit area. At the same time it causes a net increase in the JFET resistance that opposes the current flow from the channel (source) to the drain of the device.
The use of trench structures for forming power MOS devices is well known. In particular, the article “An Ultra-Low On-Resistance Power MOSFET Fabricated Using A Fully Self-Aligned Process”, by D. Ueda et al., IEEE Trans. Elect. Dev. ED-34 (1987), p. 926, discloses the structure and the fabrication process of a totally self-aligned device with the gate trench completely filled with polysilicon (deposited poly-crystalline silicon). This structure needs a photolithographic masking step for defining the source diffusion over the body. The isolation between the gate and the source is formed through selective thermal oxidization of the gate polysilicon, and it is thus self-aligned to the gate structure. It must be observed that the gate geometry in the active area imposes stringent limits to the thickness of the isolation oxide to be grown on the polysilicon.
A totally self-aligned structure with the body/source short formed along the whole perimeter by way of a trench is described in U.S. Pat. No. 5,283,201. In this case, the isolation between the gate and the source electrode is obtained by the formation of an initial spacer. This is a complicated process, and introduces a limitation in the scaling down of lateral dimensions (and to the packing) as a consequence of using an initial spacer.